Starmade Logic Tutorials

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    Tutorials #03, #04, #05, #07, #08 are out of date. i've released new versions for some of them, need to do it for the others.
    Hmm, the RS Latch tut #04 seems to work though, I tried that too, but I'm not really acquainted with electronic circuitry so maybe that was more a question of luck.
    Meanwhile I've been spitting through this thread and noticed an other version of the flip-flop with a circuit drawing, wonder if I can get that version working, I'll see tomorrow. ;)

    Greets,

    Jan
     
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    Could you make a tutorial for a incrementer please? async or synch or both ^^ I tried to make one but its seems to fail: tried your jk ff version and the one with nands instead but neither seems to work the way it should.

    thanks for the tutorials so far gj wd.
     
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    Has anyone seen a random output yet or is that not possible? Basically looking for a random pulse for design only. I don't wants my lights flashing in unison... :)
     

    Bench

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    It would be pseudo-random, i've done a little bit of it.
     
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    Is there any known problem with the loading time of many logic blocks?
    I'm building a full 8bit computer, and my RAM needs 2 or 3 minutes to load and it's only 1/4 the size of my first goal.
    It's a 64x8bit RAM at the moment.

    Is the game parsing all connections every time someone enters the sector (if it was unload before) or only on startup?
    On Startup would be ok, but otherwise would have to stop my project :(

    If i say it needs some minutes to load, that means, that no action is applied to any logicblocks until they are loaded. I can watch them getting loaded, one (1 Byte cell) by one.
     

    Bench

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    There are currently issues with excessive amounts of logic being loaded in, I've mentioned it to the team and given a build for them to test with, we have some ideas of how to optimize it, just need to work on it
     
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    takethispie

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    Knack finite oh you're making a cpu too ? :D
    unfortunatly state machine and everything with a lot of logic block don't work/are broken almost every time ....
    you should take a look at my topic "processor architecture" in the offtopic section ;)
     

    NeonSturm

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    I'm building a full 8bit computer, and my RAM needs 2 or 3 minutes to load and it's only 1/4 the size of my first goal.
    Do you use my community content RAM for this?
    • I have a new idea for doing 2-block bits (1/4 the size), but it increases read time by a factor of 2 because you have to write back the original value.
    • I wait for the new logic blocks to solve this issue.

    unfortunatly state machine and everything with a lot of logic block don't work/are broken almost every time ....
    I guess you need EEC RAM and redundant circuits :D
     
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    Do you use my community content RAM for this?
    No I don't use your RAM.
    I have looked at it after I built my own and for me, your RAM looks inefficient. :)

    I'm also waiting for the new blocks, but they will not solve anything for me, because the upcomming Flip-Flop-block needs nearly as many blocks as my current RAM-solution.

    I have reduced my RAM-Bits to two NOTs + three ANDs (adress ANDs), that's the half of the size i had as i posted here the my first post.
    With the new block, 4 blocks per bit would be possible
     

    NeonSturm

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    With the new block, 4 blocks per bit would be possible
    2 blocks for the bit and row/column addressing + 10..30% controlling logic

    You need:
    • 1x AND
    • 1x Storage (flip-flop or activation module)
    You can use the AND to reset certain columns in a row and an always-on setter to initialize the row.

    If you connect all Storage of one Column to one Activation Module, you can read values from the Storage by resetting it.
    ____

    My community content was meant as RAM, but it is more a Cache-Memory (fast read + bulk write)
     
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    Mine is a static RAM with system-registers, very fast I suppose.
    x=x+y takes two cycles (2 s)
    1.) Write y to ADD_REG
    2.) Add x and write it to x (instead of ADD_REG)

    Read and Write are separate operations, or can be done at once (transparent)
     

    NeonSturm

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    Perhaps.
    __
    For writing, you have to do:
    1. select address
    2. idle
    3. open write access
    4. close write access
    • (4 half = 2 full cycles)
    • (repeat last 2 steps for bulk write)
    If you "open/close write access" while "select address", you may override other values than the target.

    __
    For reading, you just have to:
    1. select address + start value copy (in one step)
    2. end value copy
    • (2 half = 1 full cycle)
    __
    If you not want to use write/read distinguishable access, your memory cells will be smaller,
    but you have to write the old value back:
    1. select address
    2. open read access => resets cell
    3. close read access + start value copy
    4. end value copy
    5. open write access
    6. close write access.
    • (6 half = 3 full cycles)
    __
    But you can read/write from multiple modules simultaneously which reduces the time for multiple values.
     
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    hello bench. While comeing up with ship designes I noticed that there is no way to remotly activate logic between docked ships. I was thinking maybe a remote activation beam block with a computer would be a fix for that, as long as its possible for it to hit blocks between docked ships. It may even be able to double as a remote docking beam, allowing a player to line 2 ships up and send over a activation command, telling the logic on the to be docked ship to fire back, and engage the dock. Add a shotgun puller beam and a seat to but up against and players could potentially retreive drones and make more interesting capital ship subsystems.
     

    NeonSturm

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    While comeing up with ship designes I noticed that there is no way to remotly activate logic between docked ships.
    There was no way.

    Now with rails you have the possibility to use area triggers and rails to communicate if they are in a fixed position to another. (I guess)
     

    Bench

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    wireless logic was confirmed in the last dev blog.