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    1. takethispie

      [Logic] Processors Design and Conception

      update: here comes the interrupt controller :D image of what does the Fazer-S looks like now (screenshots and not exported image option from logisim): the interrupt controller circuit: I'm going to create some programs that I will provide with the files and documentation :)
    2. takethispie

      XavLogic: 6 block inline counter circuit

      from binary to hexa it's easy but from binary -> decimal it's a little bit harder for big numbers but there is a lot less uses because there is no delay between connection wich is faster than my clock cycle x) I've never used jk counter even if I know how to make them, i'm always using counter...
    3. takethispie

      XavLogic: 6 block inline counter circuit

      the JK latches based counter work for the same reason there is no "formal logic" and "starmade logic" ^^ to count to 2^20 or 1 048 576 it would take 12 gate per bit -> 12 * 20 + 1 = 241 gate as I made a template it would be about less than 20min to make it also it can stack vertically and...
    4. takethispie

      Svens Practical Logic Tutorials

      as I said a multiple times I'm not talking about electricity or electronic, I'm talking about pure logic... a NOT gate was missing on the so that's why I thought it wasn't a memory cell but you are STILL trying to prove me wrong when I said it was a misunderstanding , the SvenCell is just a...
    5. takethispie

      Svens Practical Logic Tutorials

      Xavori I don't have time to write a full answer ( and I'm too much pissed off too), I will make a full answer when I will have time no you don't get nothing, you still get a signal wich is different with the technology used (with TTL low level is 0V - 0.8V)
    6. takethispie

      Svens Practical Logic Tutorials

      you didn't read the previous messages \( -_-)/ again it's not electricity it's logic ....and you should never ever EVER make something oscillate this way
    7. takethispie

      Svens Practical Logic Tutorials

      really good, it looks like a pulse from a waveform :)
    8. takethispie

      Svens Practical Logic Tutorials

      yes pulse is more of an event/action (low pulse -> going from 1 to 0, etc...) than an actual state so I think "low active" and "high active" sounds better excepts that, your graphical representation is really good ^^
    9. takethispie

      [Logic] Processors Design and Conception

      update: I've built a RAM chip :D it only has about 270 MB because I'm just too lazy to build the 255 modules xD each module is chained to the next wich allow me to don't use multiplexer to select a module, the lower 24bit of an adress correspond to the adress itself and the 8 upper bit...
    10. takethispie

      Svens Practical Logic Tutorials

      aaaah it change everything ! ^^ it was just pure logic, not electronic, but It wasn't clearly stated that you need to invert the AND input so I thought it was just a AND gate and an OR gate :)
    11. takethispie

      Svens Practical Logic Tutorials

      because the "RS ANDOR gate is just an AND gate ... here is the schematic with wire,input and not just the two gate : there is only two memory cell possible: RS NOR and RS NAND -> every other latches (JK, T, D) are made from these two and you can't make sequential logic without inverters...
    12. takethispie

      XavLogic: 6 block inline counter circuit

      as I said in the Sven topic RS ANDOR memory cells doesn't exists , it's a bug from starmade also your counter is pretty huge, it should need about only 30 gate to count from 0 to 15 ^^' 4 JK latches, 2 and gate and your clock = 6* 4 + 2 + your clock you need to learn ow to build the different...
    13. takethispie

      Svens Practical Logic Tutorials

      sadly RS ANDOR gate aren't memory cell , it's a starmade bug ...
    14. takethispie

      [Logic] Processors Design and Conception

      ok xD you need to learn the sequential logic (RS NOR latch, D Flip Flip, T Flip Flop, multiplexer, adder, etc) and really you shouldn't use decimal display, use hexadecimal display instead or just binary display with the adder + register it should take less than 200 gate to have a 8bit counter...
    15. takethispie

      [Logic] Processors Design and Conception

      Jaaskinal yeah I can see that, still it's good to start from the basic ^^ usually people don't even understand what I'm doing xD very cool ! but you seems to use a tremendous amount of gates, are your 7 segment displaying in decimal or hexadecimal ? what kind of design are you using ? adder +...
    16. takethispie

      [Logic] Processors Design and Conception

      hi, i'm here to share one of my passion and hobby: building processors for those who aren't familiar with this terms, the processor or Central Processing Unit ( CPU ) is the "brain" of your computer, in the center of the motherboard of your computer without a CPU, well...it isn't a computer...
    17. takethispie

      Planetoid class spaceship: the Maelstrom (progress thread)

      thank you , btw there is a whole layer of detail missing that I will make when the maelstrom will be almost finished :) yeah Karanak is one of my favorite artist when it comes to spaceship concept art ^^
    18. takethispie

      Planetoid class spaceship: the Maelstrom (progress thread)

      my biggest unfinished project the heavy-planetoid class Spyrius spaceship could make an entire planet fit inside the ship (but at the time it was still flat planets so it couldn't fit) but not the Maelstrom the name planetoid come from an old spaceship classification: the nameless ship...
    19. takethispie

      What is the largest know ship ever made?

      well 3 millions blocks is not really big ^^'
    20. takethispie

      Planetoid class spaceship: the Maelstrom (progress thread)

      don't worry I don't give a fuck about what is saying (but thank you btw ^^ ) , according to his previous posting he is not going to last long here anyway 'cause he is a troll xD