Starmade Masterclass - Learn the theory behind logic etc.

[Megacrafter127]

We'll get there eventually, have to start with the basics and work our way up.

True, however teaching circuits without the "interference" of timing is usually easier.

 

[Xavori]

I think you could save yourself a lot of extra words and video just by teaching people what each logic block does and then how to make a pulse limiter, an RSNOR memory cell, a clock circuit, and maybe a T flip-flop.

You really can do just about anything with just those tools because unlike Minecraft where you had to build AND and OR and such and couldn't crosswire things (well, not easily), Star-Made already has blocks that do that for you. You also don't necessarily need something like a JS flip-flop because activator blocks can be wired into OR blocks and each other to accomplish the same task.

For examples:

Automatic door: pulse limiter with the door slaved to the NOT and area triggers on both sides of the door

Toggle-able automatic chaff (or any weapon): Use a basic clock into an AND as well as an activator into the same AND. The AND then controls the weapons and the activator turns the system on and off.

Vertical gravity tube: Activators with gravity slaved and hooked into each other as well as a memory cell. Stick pulse limiters on those activators as well so they don't stay on and mess up the memory cell. A third activator at the top with an area trigger that resets gravity and the other input of the memory cell. The memory cell controls opening and closing a door at the top that acts as the floor.

Air lock: multiple pulse limiters into a memory cell and perhaps a few delays and lights for effect.

Keycode controled anything: I'd have to actually draw this up, but it doesn't use anything special, just requires memory cells wired into AND's to keep track of stuff and pulse limiters to keep the activators from staying on. Even getting fancy with a lock-out to prevent guessing doesn't require anything more than memory cells to track the number of failed attempts.

 

[Bench]

True, however teaching circuits without the "interference" of timing is usually easier.

True, but for more advanced circuits it's preferable to utilize pulses rather than constant on and off. As such it was necessary this early in the piece to introduce timing.

I think you could save yourself a lot of extra words and video just by teaching people what each logic block does and then how to make a pulse limiter, an RSNOR memory cell, a clock circuit, and maybe a T flip-flop.

tl;dr

I have another series that goes into the practical applications of logic, such as doors, gravity lifts, etc etc. This series is more for people who want to understand the theory behind it. The why things happen rather than just copy what i'm doing ta-da you've built it. For those that just want to learn how to build this or that, the other series is for them.

In the past three videos we've covered Activation Modules, Or Gates, Not Gates, And Gates, delay blocks, how each works and how to use them to build buttons (pulse limiter) and clocks. In the next episode we'll be covering RSNOR memory cells and probably T flip-flops as it doesn't take much to change a RSNOR into a flip-flop.

 

[rcsteiner9]

Nice video's thanks bench!

 

[Bench]

we're back with memory circuits!

 

[Megacrafter127]

we're back with memory circuits!

I do not know whether or not this one may be too high for this project of teaching the basiscs, but you should feature how to build an OR from NOTs and (N-)ANDs, and vice versa. This would in turn allow one to compress an RS-latch into 3 blocks(in cases of an inverted r input even 2 blocks).

 

[Bench]

who knows, maybe we'll just add in NOR and NAND blocks into the game.

 

[Megacrafter127]

who knows, maybe we'll just add in NOR and NAND blocks into the game.

I'd prefer XOR and odd parity gates over that, but whatever, not my game.

 

[KiloZulu]

BENCH!!!

Just want to say that your series is amazing, and I really appreciate all of the time and hard work that must go into creating these videos.

 

[Zekester81]

Yes, thanks for the series. I actually understand some more of it now and was able to build lockouts for a drone rack launching system. First time I have used AND blocks for anything where I didn't just paste a template in.

 

[Plazmatic]

I'd prefer XOR and odd parity gates over that, but whatever, not my game.

Please we need this! Currently it take 4 blocks minimum to create an XOR, there is no reason this can't be made with as simple logic as all the other gates:
//Connections is the number of logic gates connected to it
//ConnectionsOn is the number of logic gates with a high signal, or on, or '1'.

AND activation: Connections == ConnectionsOn
OR activiation: ConnectionsON != 0
XOR activation: ConnectionsON% 2 == 1


Implementing XNOR, NOR, and NAND could help performance as well, but only by a factor of two blocks in terms of updates. Still would be nice though, but XOR one blocks are damn near essential for very large logic builds.

 

[Megacrafter127]

XOR activation: ConnectionsON% 2 == 1

That is the definition of the odd-parity gate, if the one describing logic gates defined one.
When an odd-parity gate is defined, the XOR gate is defined by: NAND(Connections,ConnectionsON) & OR(Connection,ConnectionsON)
The reason being, that there are several ways to have the 2-input XOR, that produce different truth tables, when there are more than 2 inputs.

Spoiler: OR & NAND

A | B | OR | NAND | OR & NAND
0 | 0 | 0 | 1 | 0
1 | 0 | 1 | 1 | 1
0 | 1 | 1 | 1 | 1
1 | 1 | 1 | 0 | 0

Spoiler: n%2

A | B | n | n%2
0 | 0 | 0 | 0
1 | 0 | 1 | 1
0 | 1 | 1 | 1
1 | 1 | 2 | 0

 

[Plazmatic]

That is the definition of the odd-parity gate, if the one describing logic gates defined one.
When an odd-parity gate is defined, the XOR gate is defined by: NAND(Connections,ConnectionsON) & OR(Connection,ConnectionsON)
The reason being, that there are several ways to have the 2-input XOR, that produce different truth tables, when there are more than 2 inputs.

Spoiler: OR & NAND

A | B | OR | NAND | OR & NAND
0 | 0 | 0 | 1 | 0
1 | 0 | 1 | 1 | 1
0 | 1 | 1 | 1 | 1
1 | 1 | 1 | 0 | 0

Spoiler: n%2

A | B | n | n%2
0 | 0 | 0 | 0
1 | 0 | 1 | 1
0 | 1 | 1 | 1
1 | 1 | 2 | 0

Confused by what your point is here, 3+ input of XOR gate is standard defined as odd input high, Wikipedia:

"Strict reading of the definition of exclusive or, or observation of the IEC rectangular symbol, raises the question of correct behaviour with additional inputs. If a logic gate were to accept three or more inputs and produce a true output if exactly one of those inputs were true, then it would in effect be a one-hot detector (and indeed this is the case for only two inputs). However, it is rarely implemented this way in practice.

It is most common to regard subsequent inputs as being applied through a cascade of binary exclusive-or operations: the first two signals are fed into an XOR gate, then the output of that gate is fed into a second XOR gate together with the third signal, and so on for any remaining signals. The result is a circuit that outputs a 1 when the number of 1s at its inputs is odd, and a 0 when the number of incoming 1s is even. This makes it practically useful as a parity generator or a modulo-2 adder.

For example, the 74LVC1G386 microchip is advertised as a three-input logic gate, and implements a parity generator.[8]"

XOR gate - Wikipedia, the free encyclopedia

Also NAND(Connections,ConnectionsON) & OR(Connection,ConnectionsON) works in starmade right now, it is not true that it only works when odd parity is defined. This is how you make XORs right now, hence why I said " Currently it take 4 blocks minimum to create an XOR".

 

[Megacrafter127]

Confused by what your point is here, 3+ input of XOR gate is standard defined as odd input high, Wikipedia:

"Strict reading of the definition of exclusive or, or observation of the IEC rectangular symbol, raises the question of correct behaviour with additional inputs. If a logic gate were to accept three or more inputs and produce a true output if exactly one of those inputs were true, then it would in effect be a one-hot detector (and indeed this is the case for only two inputs). However, it is rarely implemented this way in practice.

It is most common to regard subsequent inputs as being applied through a cascade of binary exclusive-or operations: the first two signals are fed into an XOR gate, then the output of that gate is fed into a second XOR gate together with the third signal, and so on for any remaining signals. The result is a circuit that outputs a 1 when the number of 1s at its inputs is odd, and a 0 when the number of incoming 1s is even. This makes it practically useful as a parity generator or a modulo-2 adder.

For example, the 74LVC1G386 microchip is advertised as a three-input logic gate, and implements a parity generator.[8]"

XOR gate - Wikipedia, the free encyclopedia

Also NAND(Connections,ConnectionsON) & OR(Connection,ConnectionsON) works in starmade right now, it is not true that it only works when odd parity is defined. This is how you make XORs right now, hence why I said " Currently it take 4 blocks minimum to create an XOR".

In essence:

vs

 

[Plazmatic]

In essence:
View attachment 22364
vs
View attachment 22365

I'm still incredibly confused by what you are trying to convey. Yes, the top is a one hot detector, and the bottom is a odd parity gate, but what does that mean in the context of your original reply? Where you just stating facts or you trying to make an argument? I feel like the subject or preposition was lost in translation or something.

 

[Megacrafter127]

I'm still incredibly confused by what you are trying to convey. Yes, the top is a one hot detector, and the bottom is a odd parity gate, but what does that mean in the context of your original reply? Where you just stating facts or you trying to make an argument? I feel like the subject or preposition was lost in translation or something.

Spoiler: Small correction

The top one is odd-parity, neither of both is a one-hot detector. The bottom one has the following truth table:
A B C | R
0 0 0 | 0
0 0 1 | 1
0 1 0 | 1
0 1 1 | 1
1 0 0 | 1
1 0 1 | 1
1 1 0 | 1
1 1 1 | 0

My argument was not just adding an XOR, but adding several blocks, that behave like XOR with 2 inputs, but behave differently for more than 2 inputs, as XOR for 2 inputs can be defined in several different ways, that only differ, when expanded to more than 2 inputs. This will avoid people expecting different behaviour from an XOR with more than 2 inputs. [I personally define XOR forh N>2 as (n>0 & n<N) [n=number of active inputs, N=number of inputs], this definition however clashes with many other definitions of XOR for N>2]

 

[Plazmatic]

Spoiler: Small correction

The top one is odd-parity, neither of both is a one-hot detector. The bottom one has the following truth table:
A B C | R
0 0 0 | 0
0 0 1 | 1
0 1 0 | 1
0 1 1 | 1
1 0 0 | 1
1 0 1 | 1
1 1 0 | 1
1 1 1 | 0

My argument was not just adding an XOR, but adding several blocks, that behave like XOR with 2 inputs, but behave differently for more than 2 inputs, as XOR for 2 inputs can be defined in several different ways, that only differ, when expanded to more than 2 inputs. This will avoid people expecting different behaviour from an XOR with more than 2 inputs. [I personally define XOR forh N>2 as (n>0 & n<N) [n=number of active inputs, N=number of inputs], this definition however clashes with many other definitions of XOR for N>2]

I've never seen XOR defined as high for not getting high inputs (but at least one, which is what I think you were saying). I'm not sure I see the practical application of a logic gate that makes sure that not all inputs are high, and at least one is high, however it wouldn't hurt to add that as well. I didn't realize this is what you were talking about because I didn't look closely at the truth table.

One hot is easy to add,

XOR odd parity activation: ConnectionsON% 2 == 1

XOR one hot activation: ConnectionsON == 1

Looking at google, it seems your interpretation of XOR is non existent, I've never encountered this definition at university, and people only mention the above two definitions, but I didn't realize this was the definition of what happens when you expand the four block XOR gate with (OR + NAND). It is still pretty simple to implement.

XOR 4GATE Expanded: (ConnnectionsON % Connections) != 0

I'd like to know what you use that one for.

 

[Megacrafter127]

I've never seen XOR defined as high for not getting high inputs (but at least one, which is what I think you were saying). I'm not sure I see the practical application of a logic gate that makes sure that not all inputs are high, and at least one is high, however it wouldn't hurt to add that as well. I didn't realize this is what you were talking about because I didn't look closely at the truth table.

One hot is easy to add,

XOR odd parity activation: ConnectionsON% 2 == 1

XOR one hot activation: ConnectionsON == 1

Looking at google, it seems your interpretation of XOR is non existent, I've never encountered this definition at university, and people only mention the above two definitions, but I didn't realize this was the definition of what happens when you expand the four block XOR gate with (OR + NAND). It is still pretty simple to implement.

XOR 4GATE Expanded: (ConnnectionsON % Connections) != 0

I'd like to know what you use that one for.

I don't use it very often, as most of my uses of XOR only have 2 inputs, thus making the extendable definition irrelevant. However, it can be used to detect whether or not a multi-bit integer is at a value, that may cause over or underflow[0-1=N; N+1=0 //N=(2^n)-1 //n...number of bits], so long as one does not care which case it is. In addition, it can be used to check whether or not an array of sensors all have the same output, by feeding all of them into the expanded 4gate, and negating the output of the extended gate. This 5Gate XNOR is essentially a check for equality of all inputs, regardless of their value.

 

[Plazmatic]

I don't use it very often, as most of my uses of XOR only have 2 inputs, thus making the extendable definition irrelevant. However, it can be used to detect whether or not a multi-bit integer is at a value, that may cause over or underflow[0-1=N; N+1=0 //N=(2^n)-1 //n...number of bits], so long as one does not care which case it is. In addition, it can be used to check whether or not an array of sensors all have the same output, by feeding all of them into the expanded 4gate, and negating the output of the extended gate. This 5Gate XNOR is essentially a check for equality of all inputs, regardless of their value.

It would be nice to have all these blocks added, it could potentially reduce the lag of a lot of systems by several factors by reducing the blocks and computation time involved in the circuits. I hope they do end up adding these, and if it isn't already like this (I rarely play non creative mode) I hope they make these logic gates a general resource, so the block that makes the OR is the same that makes the AND, and they all feed from one resource pool.

 

[GalactusX]

if anyone have any dude how logic gates work, a picture is worth a thousand words

and how to make all the gates using only NAND gates

... this is the reason why more logical blocks that implement those already in the game are needed ...

- less space needed to do the same thing
- more complex operations using fewer blocks