While this could be useful it might be better to have a min and max amount of delay that you can have on one block. (Kind of like a red stone repeater) because if you could just input a number into a GUI we could end up with systems that have hour long delays witch could potentially cause lag.
I have experimented with the logic system a little and know how it updates, the longer the delay the less lag is to be expected. I'm more worried about people setting the delay to 0.
I have experimented with the logic system a little and know how it updates, the longer the delay the less lag is to be expected. I'm more worried about people setting the delay to 0.
Not quite: after an input change each delay block creates a new logic update after a given amount of time.
E.g. link one Activator and one NOT gate in the following order: Activator>>>NOT>>>Activator
After starting the circuit by activating the trigger module, it will unlikely pulse, because none of these modules cause a logic update(with the exception of the update triggered by pressing R on them). The DELAY on the other hand creates a logic update after the input has changed and the given amount of time has passed. If the time is set to 0 for whatever reason, a clock with this DELAY module will cause anotherlogic update immedeatly, causing the CPU load to go to 100%(just like any
A variable delay would be nice, especially if really long delays where possible to make clocks. But more important than that would be the possibility of having shorter delays, since the current delay is way too long for fancy blinking stuff.
If you have an activation block which triggers 2 delay blocks which both trigger the activation block, you will soon have infinite circuit calculations, or not?
Independent of delay-time; You just need more delay blocks the greater the delay.
If you have an activation block which triggers 2 delay blocks which both trigger the activation block, you will soon have infinite circuit calculations, or not?
A standard clock(NOT<==>DELAY) actually works better, than a 2DELAY+Activator clock, because the latter can be stopped by having the Activator active when it shall not be active, or inactive, when it shall be active. The NOT-DELAY clock cannot be stopped without interrupting the signal between the NOT and the DELAY(which can be done using an OR or an AND).
And as long as the delay lasts long enough(which it currently does), the CPU has no problems.
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