I have experimented with the logic system a little and know how it updates, the longer the delay the less lag is to be expected. I'm more worried about people setting the delay to 0.we could end up with systems that have hour long delays witch could potentially cause lag.
Ah I see.. Never thought of that issue. Setting the delay to zero erases the point of delay blocks.I have experimented with the logic system a little and know how it updates, the longer the delay the less lag is to be expected. I'm more worried about people setting the delay to 0.
Not quite: after an input change each delay block creates a new logic update after a given amount of time.Ah I see.. Never thought of that issue. Setting the delay to zero erases the point of delay blocks.
while(true) {}
A standard clock(NOT<==>DELAY) actually works better, than a 2DELAY+Activator clock, because the latter can be stopped by having the Activator active when it shall not be active, or inactive, when it shall be active. The NOT-DELAY clock cannot be stopped without interrupting the signal between the NOT and the DELAY(which can be done using an OR or an AND).If you have an activation block which triggers 2 delay blocks which both trigger the activation block, you will soon have infinite circuit calculations, or not?