My brain is not agile enough any more to handle many of the complexities of logic circuits. This is the hack job I did to control a docked power module. It is built this way mostly to be easy for me to follow the logic of. While any of the bottom delays are active, they will activate the lower 'or' block that activates the bottom power supply beam computer. While any of the top delays are active, they will activate the upper 'or' block that activates the top power supply beam computer. All the delays feed into another 'or' block which in theory always stays 'on/high'. If for some reason however due to a reboot or whatever, the circuit is not working, that 'or' block will be off, which will activate the 'not' block to the left, which will restart the clock.
I am pretty sure this is not the ideal setup, but this is as good as my limited understanding of logic circuits can do at the moment. Sven the Slayer has
a video tutorial on clocks in which he describes what would clearly be a better clock, but despite watching it several times, I cannot understand what he has built or how it functions (my brain is not what it used to be).
Anyone care to tell me what I should do differently? I realize I could likely do away with one of the rows of delay blocks and simply invert the signal for the other beam, but the one presented is both easier to understand for my brain and visually more pretty.
I haven't tested the following 3-module logic in-game yet, having only used a logic simulator, but it reduces the logic to 10 blocks, and should be adequately fail-proof.
1. Master Control Switch (Activator Block)
2. Failsafe AND gate
3. Master Control Failsafe OR gate
4. Pre-delay AND gate
5. Delay gate
6. Post-delay NOT gate
7. Computer Controller 1 AND gate
8. Computer Controller 2 AND gate
9. Failsafe OR gate
10. Failsafe NOT gate
A. Control Module (using blocks 1-3):
slave both (2) and (3) to (1) (Both the AND and OR gates should receive a signal from the master control switch.)
slave (2) to (3) (The OR gate should now receive a signal from both the master control switch and the AND gate.)
B. Alternating Clock Module (using blocks 4-8):
slave (5) to (4) (AND gate drives the delay block)
slave (7) to (5) (DELAY gate drives the AND gate for computer 1)
slave (6) to (5) (DELAY gate drives the NOT gate for computer 2. Alternatively, slave (6) to (7) instead to have the computer 1 AND gate drive the computer 2 NOT gate.)
slave (8) to (6) (NOT gate drives the AND gate for computer 2)
slave (4) to (6) (NOT gate drives the pre-delay AND gate, restarting the cycle)
C. Fail Detection Module (using blocks 9 and 10):
slave (10) to (9) (OR gate drives the NOT gate, so that if both OR signals are false, the NOT gate creates a true signal.)
D. Overall Module Linking:
A -> B:
slave (4) to (3) (The OR gate should drive the pre-delay AND gate)
slave (7) to (3) (The OR gate should help drive the computer 1 AND gate)
slave (6) to (3) (The OR gate should help drive the computer 2 NOT gate)
(This allows the master control switch to shut down the entire operation without the failsafe restarting it again.)
B -> C:
slave (9) to (7) (The computer 1 AND gate drives the failsafe OR gate)
slave (9) to (8) (The computer 2 AND gate drives the failsafe OR gate)
(This allows the failsafe module to recognize when both outputs are off together, suggesting a fault.)
C -> A:
slave (2) to (10) (The Failsafe NOT gate drives the Control Module AND gate)
(This allows the failsafe module to restart the master control in case of a fault.)
Finally, slave the support effect control computers to blocks (7) and (8), respectively. (The controller AND gates will alternately drive the support control computers.)
At this point, if both computer controllers are off, suggesting a problem, the failsafe module (C) generates a positive signal, restarting the cycle at gate (2). You may also want to implement reset links from a delay-and-not pair of blocks running off the Failsafe NOT gate to reset all the gates along the Clock module (B), which will bring the block count up to 12. If implementing such a reset, the link from module C (failsafe) to module A (master control) should go from the failsafe reset Delay block (instead of the Failsafe NOT block) back to Module A, to avoid timing problems with the reset.
