So, I've been trying to make Conway's Game of Life in logic, and in doing so, I've noticed a very significant problem with logic. There has previously been a thread on this very matter, the Instant Pulses thread. The reason I decided to make Conway's Game of Life, is because I saw another person who'd made it, except it was obscenely lag inducing, so I thought I'd give it a try, to see if I can bypass this lag. There is a way, but the games own logic system is preventing it.
This is the section in which I'll explain the logic, to help both understanding and explaining the problem. I will use the RAM to demonstrate.
This it 8 bits (1 byte) of RAM, which will compress all signals to the left, to allow for the counting of x amount of signals received.
For this, I have activate the first, and fifth bit. What should happen, is the fifth bit is moved down to the second, yet this fails to happen;
Instead of only leaving the second bit activated, it keeps all bits that it traveled through active. In order to understand what is meant to be happening, I'll use 3 spread out bits.
1A, 3A, and 5A are Flip Flops, and these are used to store the data.
1B and 4B are NOT signals, these activate whenever its respective Flip Flop is off.
3C and 5C are AND signals, these require the NOT signals, as well as their respective Flip Flops (3A/5A). The AND signal triggers the next Flip Flop down, in 3C's case, the next Flip Flop down is 1A.
The AND signal also triggers the Buttons (2C/6C) which will de-activate the original Flip Flop.
The Button down the bottom, is used solely to control when the compression begins.
All of this combined, should allow a signal to be moved from say 5A, down to 1A, while leaving both 3A and 5A deactivated.
So we have 5A on, while the other Flip Flops are off. Lets trigger the compression.
Now, 5A does in fact turn off, and the signal successfully manages to get to 1A, however, it leaves 3A on in the process. The reason for this, is the Instant Pulses that were talked about earlier.
5C is activated at the trigger, and sends the signal both to 6C, and 3A, 3A becomes active, and the Button deactivates 5A. This causes the next AND signal to do the same, and activates 1A. When 2C is activated, it deactivates 3A, but because of the fact that all of this happens in the single process, it allows the AND signal to keep 3A on, before it's even turned off, causing 3A to remain on.
Not only that, but this could cut down on some serious lag, caused by an excess amount of logic blocks. As before, I mentioned that I started this project in an effort to try and make an optimized/less laggy version, the reason the original caused so much lag, is because of the sheer number of logic blocks he needed. He had to have each cell (Which can go up to the hundreds) process the adjacent cells, and change according to it. The system I'm designing, would only use the cells to store data on adjacent cells, and have one CPU process it, and send the change. This system immediately cuts down on a ridiculous amount of blocks, thus saving quite a lot of lag.
If the system was in place, the RAM I demonstrated would actually work, and look like this:
So that's my suggestion to improve logic, hopefully my explanations were sufficient. :p
The Logic
This is the section in which I'll explain the logic, to help both understanding and explaining the problem. I will use the RAM to demonstrate.
This it 8 bits (1 byte) of RAM, which will compress all signals to the left, to allow for the counting of x amount of signals received.
For this, I have activate the first, and fifth bit. What should happen, is the fifth bit is moved down to the second, yet this fails to happen;
Instead of only leaving the second bit activated, it keeps all bits that it traveled through active. In order to understand what is meant to be happening, I'll use 3 spread out bits.
1A, 3A, and 5A are Flip Flops, and these are used to store the data.
1B and 4B are NOT signals, these activate whenever its respective Flip Flop is off.
3C and 5C are AND signals, these require the NOT signals, as well as their respective Flip Flops (3A/5A). The AND signal triggers the next Flip Flop down, in 3C's case, the next Flip Flop down is 1A.
The AND signal also triggers the Buttons (2C/6C) which will de-activate the original Flip Flop.
The Button down the bottom, is used solely to control when the compression begins.
All of this combined, should allow a signal to be moved from say 5A, down to 1A, while leaving both 3A and 5A deactivated.
So we have 5A on, while the other Flip Flops are off. Lets trigger the compression.
Now, 5A does in fact turn off, and the signal successfully manages to get to 1A, however, it leaves 3A on in the process. The reason for this, is the Instant Pulses that were talked about earlier.
5C is activated at the trigger, and sends the signal both to 6C, and 3A, 3A becomes active, and the Button deactivates 5A. This causes the next AND signal to do the same, and activates 1A. When 2C is activated, it deactivates 3A, but because of the fact that all of this happens in the single process, it allows the AND signal to keep 3A on, before it's even turned off, causing 3A to remain on.
The Suggestion
I propose, that rather than having all changes processed simultaneously, that the changes take effect step by step. Doing this, would allow the AND signal to actually deactivate, before the Button deactivates the Flip Flop. This change will allow circuits to work much better/fluidly, as if they were real life circuits. Since electricity isn't additive or instantaneous, logic signals should work in the same way, as to allow far better/more complicated circuits, which could even involved building an entire computer, within the game.
Not only that, but this could cut down on some serious lag, caused by an excess amount of logic blocks. As before, I mentioned that I started this project in an effort to try and make an optimized/less laggy version, the reason the original caused so much lag, is because of the sheer number of logic blocks he needed. He had to have each cell (Which can go up to the hundreds) process the adjacent cells, and change according to it. The system I'm designing, would only use the cells to store data on adjacent cells, and have one CPU process it, and send the change. This system immediately cuts down on a ridiculous amount of blocks, thus saving quite a lot of lag.
If the system was in place, the RAM I demonstrated would actually work, and look like this:
So that's my suggestion to improve logic, hopefully my explanations were sufficient. :p