Bug Flip Flop delayed output Issue

    AtraUnam

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    The output of flip-flops appears to change when put through a delay despite the fact that the logic system involved can be exactly the same:



    Here a pair of flip-flops paired with not-gates act as a looping counter with each and-gate being an output. By placing a delay after each and gate we can see that the output of the logic changes when delayed. This occurs with other logic blocks (including wireless blocks) however it is only readily visible when slowed down with delays.

    http://bugs.star-made.org/issues/2043

    Download to logic provided as requested: http://www.mediafire.com/download/9z2ldth477g2c2t/Flip-flop+bug.sment
    Mediafire used due to inbuilt uploader not playing nice, alternative download available in bug tracker.
     
    Last edited:

    AndyP

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    Thank you for adding the blueprint, we will look into it.

    - Andy
     
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