Binary counter for long delays or complex timings

[Quoa]

Hello everyone. I'm more or less brand new to StarMade and I've been really enjoying playing around with logic. Recently I've been working on a circuit using a binary counter made with a clock and a string of flip flops to replace delay blocks for particularly long delays and I plan to eventually use it for more complicated sequences once I find an application.

Here's a simple version of the circuit:

In this case it just turns on the stack of lights when the counter hits 20 (so approximately 10 seconds) and then resets counter to start the cycle over producing a short pulse every 10 seconds.

The problem I've been running into is that the counter is producing junk signals. In the example without the delay block coming out of the final AND the counter will reset well before it ever reaches 20, or will simply hang at 10 and no longer advance.

When feeding the AND block into another flip flop with the intent to produce a 10 second on 10 second off cycle the lights will pulse in an odd pattern. Again a delay block after the AND was invaluable in removing the junk signals, although in this case it produces a half second delay that needs to be accounted for by moving the triggering input to 19.

So as of right now the final version of the test circuit uses a delay after every flip flop to remove the rest of the pulses. The same caveat about adjusting which out puts are chosen aside this works well and has yet to produce any unexpected results. The extra blocks are a shame but it's still a significant savings over using delay blocks, breaking even around a 10 second delay or so if my math is right.

Anyone have any suggestions on how I could improve this? Specifically either by reducing the block count or eliminating the half second delay on start up?

 

[HolyCookie]

Quoa I have 2 possible solutions for you, because I'm not sure where the junk problem is coming from.

solution 1, a very easy solution but most likely not the problem. all logic gates have mini delays in them (except delay blocks they have 0.5 delay)
this delay may break your circuit, I used to put a delay somewhere in the end to fix the problem, later using this thread:
https://starmadedock.net/threads/instant-pulses-and-some-starmades-logic-details.8117/
basically, try using an or-gate instead of a delay block.

If that didn't work, you might have some double signal problem or something. All I can say to that is check if the signals from the delay to the and-gates are correct. you can check this by taking 1 button, connect it with the first delay block/connect it to all delay blocks.
then keep pressing it to see if your and-gates only activate at 1 moment or if they activate at multiple moments. if they activate at multiple moments, keep pushing the button until you are at the point that you want (10 seconds point) then look at the flip-flops. make sure that the and-gates will only go on according to the flip-flops example: and-gate "on" when flip-flop 1 "off" and flip-flop 2 "off" and flip-flop 3 "on"
hope you understand it, let's just hope it's solution 1 xD

 

[Quoa]

solution 1, a very easy solution but most likely not the problem. all logic gates have mini delays in them (except delay blocks they have 0.5 delay)
this delay may break your circuit, I used to put a delay somewhere in the end to fix the problem, later using this thread:
https://starmadedock.net/threads/instant-pulses-and-some-starmades-logic-details.8117/
basically, try using an or-gate instead of a delay block.

I believe the noise I described on the circuit is the instant pulses described in the thread you linked propagating through the circuit. Which makes sense because the counter relies on the flip flops going back and forth before coming to a stable position at each value. The last one that I posted works fine, apart from a short delay between starting the clock and the cycle starting. Unlike the logic gates, the delay blocks don't seem to pass along pulses shorted than a full pulse allowing them to act as a filter for the circuit. I'm working on trying to reproduce a real world synchronous counter based on some real world descriptions of how to do it but haven't yet had much luck, between the peculiarities of StarMade and my only formal education on the topic being a half forgotten high school electronics class fifteen years ago.

So playing with the circuit I tried a few more things to eliminate the noise, including your first suggestion, and it turns out that your OR suggestion works. In fact it seems to work with all three logic gates, placed on either side of the flip flops in the circuit. Doing it with NOTs produces the potentially interesting result of having a decrementing and incrementing timer running at the same time synchronized to one another, and changes the resting state to a high signal.



There's still a little noise on the circuit, so the reset button needs a delay block, otherwise the count will reset at 15 but these versions have it triggering the test light properly so I expect it will work for most purposes. I also added a NOT between the clock toggle and the reset button so that the sequence will start from the beginning any time the clock is stopped and started again.

Thanks for your help!

 

[HolyCookie]

Quoa This "noise" signal, do you mean 2+ rapid signals that pass through a gate?
like you should have a solid signal with max 2 signals per second but you got more than 2 signals per second?
If this is true, try replacing the delay with an activator, the activator acts different than all other gates, can't really explain what it is.
If this wasn't the meaning of a noise signal, please explain :D

 

[Quoa]

Quoa This "noise" signal, do you mean 2+ rapid signals that pass through a gate?

That's exactly what I mean. Presumably they're happening constantly as the counter runs. At a guess adding the extra line of logic gates is pulling them a bit more out of sync and keeping them from passing the AND gate that triggers the light. So the reason it stops at 15 without the delay should be that it's started to carry to the 16s place before the other bits have cleared, though the exact timing sometimes seems to drift between logins so it's probably a bit more chaotic than that.

I tried switch to an activation module, plus a delay and a button to toggle it back off for the reset like you suggested and it does stop the premature resets. While I was at it I found what I feel may be a better solution.
Using a NOT and an OR to create a NOR testing the bits that should be off and fed into the AND so it only triggers when the exact value is showing (rather than greater than or equal to as before) seems to filter out the junk signals. I thought I'd tried this earlier but it was late at night so I must have done it wrong. Seems to be stable. For just a single long delay this is the smallest block count I've gotten so far. For longer sequences it will probably end up using more blocks but I expect this is less likely to send out incorrect signals.